With the advent of the lnternet-of-Things (1oT) era, sensor nodes are required in almost all fields to achieve a better interaction between humans and the environment. Piezoelectric energy harvester (PEH), which exhibits an equivalent electrical model of an AC current source /P in parallel with the inherent capacitor CP, is a promising technology to resolve the energy problem of such sensor nodes. Recently, inductor-based rectifiers, capacitor-based rectifiers and hybrid rectifiers have been proposed to improve the energy extraction efficiency of PEH devices [1]–[5]. However, these structures all require the aid of additional capacitors or inductors to achieve bias-flip operation, as illustrated in Fig. 1. These extra passive devices are typically large, which can be a major bottleneck in system-volumeconstrained applications such as MEMS [4]. In response to the above problem, this work proposes a novel 8-phase self bias-flip PEH interface with charge recycling and reusing (SBFRR). By using the C P of 4 PEHs as flipping capacitors, this scheme achieves a high voltage flipping efficiency without using extra energy reservoirs. The 4 C P can also serve as flying capacitors to achieve switched-PEH DC-DC (SPDC) conversion for MPPT, while maintaining a MOPIR of >3.5× with a PEH input voltage (Vp) from 0. 78Vto4.9V.@en

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( CP ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- μ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 × . In addition, with the four CP serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of > 3.5 × can be maintained with a PEH input voltage from 0.78 to 4.9 V.@en

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( CP ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- μ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 × . In addition, with the four CP serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of > 3.5 × can be maintained with a PEH input voltage from 0.78 to 4.9 V.@en

This article proposes a novel eight-phase self-bias-flip piezoelectric energy harvesting interface with charge recycling and reusing (SBFRR) and a switched-piezoelectric energy harvester (PEH) dc–dc (SPDC) converter. The proposed scheme innovatively utilizes the inherent capacitors ( CP ) of four PEHs as energy sources, flying capacitors, and flipping capacitors for time-sharing reuse to achieve both a high-voltage flipping and dc–dc conversion efficiency, while avoiding the use of extra energy reservoirs. The design is fully integrated and fabricated in standard 0.18- μ m CMOS. Measurement result demonstrates that the voltage flipping efficiency of up to 80% is achieved. Compared with the ideal full-bridge rectifier (FBR), the measured maximum output power improving rate (MOPIR) can be increased to 4.88 × . In addition, with the four CP serving as flying capacitors to achieve SPDC conversion for maximum power point track (MPPT), an MOPIR of > 3.5 × can be maintained with a PEH input voltage from 0.78 to 4.9 V.@en