Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

Journal article (2008)
Department
Microelectronics & Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2008 IEEE
Dark current CMOS image sensor (CIS) Four–transistor pixel Hole accumulation diode Imager Pinned photodiode (PPD) Well capacity
More Info
expand_more

Published Date

01-04-2008

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Source:

IEEE Electron Device Letters, 29 (4), 2008

ISSN:

IEEE

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics & Computer Engineering

Abstract

This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 ?m CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attributed to the accumulated holes and the increased potential barrier near the PPD, respectively.

Files

Mheen2008.pdf
(pdf | 0.244 Mb)