Orientation-and-Location Controlled Single-Grain TFTs on Glass Substrate

Abstract

Location controlled single-grain TFT by ?-Czochralski process has attracted a lot of interest due to its high field effect mobility which is comparable to SOI. However, the major challenge is the random orientation of the grains due to the lack of seed layer to control the orientation. This will result in poor device uniformity and limit its further application such as 3D-ICs or System-on-Glass. This thesis presents different methods to control the orientation of single-grains. The proposed methods can achieve grains with (111), (110) and (100) orientations. (100) and (110) single-grain TFTs shows not only high electron and hole mobilities, but also high uniformity which approaches to that of SOI. Moreover, the devices show more stable performance than poly-Si TFTs under different electrical. Single-Grain Ge TFTs by ?-Czochralski process shows better device performance than traditional Ge MOSFET fabricated on single-crystalline Ge wafer. It is also very promising to fabricating Ge MOSFET by ?-Czochralski process due to its unique process. Chapter 1 provides an overview of different TFT technologies and the challenges associated with location-controlled single-grain TFT by the ?-Czochralski process. By studying the limitation of continuous downscaling the device dimension, it has been explained how the ?-Czochralski process can be used for future 3D-ICs and System-on-Glass. The challenges on ?-Czochralski process for these applications are brought out and the motivation of this thesis is proposed. Chapter 2 proposes to epitaxial grow (111) oriented Si on (0001) oriented InGaZnO (IGZO). Their advantages and drawbacks are extensively discussed. The mechanism has been addressed. Also to grow (0001) oriented InGaZnO on SiO2 has been proposed by applying excimer layer. Chapter 3 described a new approach to grow both (100) and (110) oriented Si by Metal-Induced-Lateral crystallization (MILC). The mechanism of growing (100) orientated Si is due to high tensile stress at the corner of rectangular Ni pattern. And (110) oriented Si grows from the side of rectangular Ni pattern. However, the proposed method will introduce Ni contamination problems. Chapter 4 proposed a novel process to reduce Ni contamination below SIMS detection limit. (100) and (110) oriented single-grain TFT has been fabricated by combining MILC and µ-Czochralski process. Field-effect mobility of n-channel transistor is 998cm2/Vs for (100) SG-TFTs and 811cm2/Vs for (110) SG-TFTs. Field-effect mobility of the p-channel transistor is 292cm2/Vs for (100) SG-TFTs and 429cm2/Vs for (110) SG-TFTs. The orientation and location controlled SG TFT shows remarkable stability under different electrical stress. This process is very promising to integrate high performance RF circuits, logic circuit and memories directly on glass substrate Chapter 5 described a new technique to fabricate Ge transistors with world record high mobility and on-off ratio. By using capping oxide during laser crystallization, the GeO is melted and interface between gate oxide and Ge channel region has been improved. By replacing Ge with doped Si at source and drain, high tensile stress has been introduced and mobility has been greatly increased. Moreover, the dopants diffusion from source and drain to channel region has been suppressed. Therefore, a high on-off ratio has been achieved. Chapter 6 presents the conclusions and recommendations of this research. The most important conclusion is that the orientation- and location-controlled single-grain TFT can achieve high performance devices, which are superior to SOI. By making use of these devices, it is promising to fabricate 3D-ICs monolithically.