A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Gong, J. (TU Delft OLD QCD/Charbon Lab)
Sebastiano, F. (TU Delft (OLD)Applied Quantum Architectures)
Charbon-Iwasaki-Charbon, E. (Swiss Federal Institute of Technology; Intel Labs)
Babaie, M. (TU Delft Electronics)

2020

This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and reducing the duty cycle of the sampling clock. Without requiring any RF dividers, a 50 μW frequency tracking loop is also introduced to robustly lock the CSPLL to a 100 MHz reference. Fabricated in 40-nm CMOS, the 0.13 mm2 CSPLL achieves an RMS jitter of 50 fsec at 11.4 GHz while consuming 5 mW.

charge-sampling phase detector
Charge-sampling PLL
divider-less frequency tracking loop
low-jitter

http://resolver.tudelft.nl/uuid:50775705-f469-4e73-a110-fee3001a0bbb

https://doi.org/10.1109/RFIC49505.2020.9218380

IEEE, Piscataway, NJ, USA

9781728168098

RFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium

2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020, 2020-08-04 → 2020-08-06, Virtual, Los Angeles, United States

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, 1529-2517, 2020-August

Accepted Author Manuscript

Institutional Repository

conference paper

© 2020 J. Gong, F. Sebastiano, E. Charbon-Iwasaki-Charbon, M. Babaie