Analog Integrated Circuit and System Design for a Compact, Low-Power Cochlear Implant

Abstract

Cochlear Implants (CIs) are prosthetic devices that restore hearing in profoundly deaf patients by bypassing the damaged parts of the inner ear and directly stimulating the remaining auditory nerve fibers in the cochlea with electrical pulses. This thesis describs the electronic circuit design of various modules for application in CIs in order to save area, reduce power consumption and ultimately move towards a fully implantable CI. To enhance the perception of tonal languages (such as Thai and Chinese) and music, an effort to realize the speech processor in a CI that imitates the inner hair cells and the auditory nerve behaviour more precisely should be made. According to recent physiological experiments, the envelope and phase of speech signals are required to enhance the perceptive capability of a CI implanted patient. The design of an analog complex gammatone filter is introduced in order to extract both envelope and phase information of the incoming speech signals as well as to emulate the basilar membrane behavior. A subthreshold Gm ? C circuit topology is selected in order to verify the feasibility of the complex gammatone filter at very low power operation. Several speech encoding strategies like continuous time interleaved sampling (CIS), race-to-spike asynchronous interleaved sampling (AIS), phase-locking zero-crossing detection (PL-ZCD) and phase-locking peak-picking (PL-PP) are studied and compared in order to find a compact analog speech processor that allows for full implantation and is able to convey both time and frequency components of the incoming speech to a set of electrical pulse stimuli. A comparison of the input and reconstructed speech signals in terms of correlation factor and hardware complexity pointed out that a PL-PP strategy provides a compact solution for the CI electronic hardware design since this strategy does not require a high precision envelope detector. A subthreshold CMOS peak-instant detector to be used in a PL-PP CI processor has been designed. Circuit simulations, using AMIS 0.35 um technology, show that the proposed detector can be operated from a 1.2 V supply and consumes less than 1 uW static power for detecting a 5 kHz input signal. The output signal of the detector together with the input signal amplitude (the output of the band-pass of each channel) is expected to be used as control parameters in a stimulator for apical cochlear electrodes. To design stimulators that are implanted inside the body, there are very strict requirements on the size and power consumption. Therefore, it is important to convey as much charge as possible into the tissue while using an as low as possible supply voltage to minimize power consumption. A novel method for maximizing the charge transfer for constant current neural stimulators has been presented. This concept requires a few additional current branches to form two feedback loops to increase the output resistance of a MOS current mirror circuit that requires only one effective drain-source voltage drop. The main benefit we achieve for neural stimulation is the larger amount of charge that can be conveyed to the stimulation electrode. In other words, for the same amount of charge required, the supply voltage can be reduced. Also, a compact programmable biphasic stimulator for cochlear implants has been designed by using the the above concept and implemented in AMS 0.18 um high-voltage CMOS IC technology, using an active chip area of only 0.042 mm^2. Measurement results show that a proper charge balance of the anodic and cathodic stimulation phases is achieved and a dc blocking capacitor can be omitted. The resulting reduction in the required area enables many stimulation channels on a single die. As the work laid out in this thesis produced only stand-alone modules, future work should focus on combining all these modules together to form an analog CI processor suitable for a fully implantable cochlear implant.