Embedded System Design for Bioelectronic Interface to Sensory Cortex

More Info
expand_more

Abstract

Visual perception is a pillar of human life. Visual impairment, therefore, has a severe impact on the quality of life. The Bioelectronic Interface to Sensory Cortex (BISC) project is aimed at building a system capable of both recording and stimulating neurons in order to remedy visual impairment. The proposed BISC system consists of three components: a brain implantable chip, a relay station, and a base station. The so-called BISC chip implanted atop the brain can electrically interact with neuron populations for the purpose of recording and stimulation. The relay station transfers data to and from the BISC chip wirelessly, and is composed of an embedded system and a printed circuit board (PCB) that the user can wear on the outer side of the head. The base station connects to the relay station via Wi-Fi in order to communicate with the BISC chip, and is represented by a desktop computer. In this work we focus on the design of the embedded system in the relay station. We compare networking protocols and perform bandwidth measurements on the Wi-Fi link to explore the design space. A minimum bandwidth of 83.2 Mbit/s is required to support the BISC chip data rate. Our C++ software infrastructure for networking reaches an attainable bandwidth of about 90 Mbit/s using 5 GHz Wi-Fi. A C++ Application Program Interface (API) is developed in order to communicate with the BISC chip from the base station, through the relay station. The API enables a base station user to send instructions to the BISC chip in order to set it up for recording or stimulation. Responses and recordings from the BISC chip are transferred to the base station for analysis. A digital module for the relay station is designed in order to relay data to and from the BISC chip. The digital module is written in SystemC and synthesized for FPGA fabric using a high- level synthesis tool. The module successfully interfaces to the PCB and is capable of relaying 83.2 Mbit/s of data from the BISC chip to memory. Additionally, embedded software to control the digital module is developed. The embedded software is capable of delivering BISC chip instructions to the module, and can read responses and recordings from memory in order to make them available to the API. By testing in vitro, the BISC system is demonstrated to be functional with acknowledgements sent out by the BISC chip in response to commands sent from the base station. Recordings can be stored on the relay station or transferred wirelessly to the base station in real-time.

Files

Master_Thesis_Embedded_System_... (pdf)
(pdf | 20.1 Mb)
- Embargo expired in 30-07-2021