Print Email Facebook Twitter High Speed and Wide Bandwidth Delta-Sigma ADCs Title High Speed and Wide Bandwidth Delta-Sigma ADCs Author Bolatkale, M. Contributor Makinwa, K.A.A. (promotor) Breems, L. (promotor) Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics Date 2013-10-22 Abstract This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CT??) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this thesis investigates excess loop delay compensation techniques at the system level which enable the design of a wide-bandwidth (BW), high-dynamic range (DR) CT?? modulator with good power-efficiency. This thesis demonstrates that CT?? ADCs implemented in nanometer CMOS are a power efficient alternative to Nyquist-rate ADCs for wide signal bandwidths (greater than 100MHz) and high dynamic ranges (more than 12-bit). The performance of a high-speed multi-bit CT?? modulator is often limited by the dynamic errors present in the feedback DAC. The applicable correction/calibration techniques are limited due to the modulator stability requirements. We have implemented a dynamic error correction technique which not only experimentally quantifies the level of dynamic errors but also improves the dynamic performance of the modulator. Subject ADCCMOSDelta-SigmaSigma-DeltaICHigh-speedCommunicationPower efficient To reference this document use: https://doi.org/10.4233/uuid:9d1057e0-99ea-408a-afe8-8b97a4dbf49a Publisher Ipskamp Drukkers B.V. Embargo date 2016-10-22 ISBN 9789461918772 Part of collection Institutional Repository Document type doctoral thesis Rights (c) 2013 Bolatkale, M. Files PDF 198092-L-DIGITAAL-bw-Bolatkale.pdf 5.56 MB Close viewer /islandora/object/uuid:9d1057e0-99ea-408a-afe8-8b97a4dbf49a/datastream/OBJ/view