This thesis describes the theory, design and implementation of a high-speed, high-performance continuous-time delta-sigma (CT??) ADC for applications such as medical imaging, high-definition video processing, and wireline and wireless communications. In order to achieve a GHz clocking speed, this thesis investigates excess loop delay compensation techniques at the system level which enable the design of a wide-bandwidth (BW), high-dynamic range (DR) CT?? modulator with good power-efficiency. This thesis demonstrates that CT?? ADCs implemented in nanometer CMOS are a power efficient alternative to Nyquist-rate ADCs for wide signal bandwidths (greater than 100MHz) and high dynamic ranges (more than 12-bit). The performance of a high-speed multi-bit CT?? modulator is often limited by the dynamic errors present in the feedback DAC. The applicable correction/calibration techniques are limited due to the modulator stability requirements. We have implemented a dynamic error correction technique which not only experimentally quantifies the level of dynamic errors but also improves the dynamic performance of the modulator.