Integrating a Neuron Network application into a ZYBO Zynq-7000 development board with an AXI-Bus interface

Abstract

In order to verify an application with a simulation, increasing the simulation speed is important. An Inferior Olivary Nucleus (ION) network has been implemented in a SystemC language and its simulation verified by a SystemC testbench. The goal of this thesis is to integrate the ION application into an FPGA in order to increase its simulation speed by using the hardware. In addition, to verify the integrated ION in the FPGA, an ARM processor is used for communication between a PC and the ION. A Zybo development board combines the capability of software programming in an ARM-based processor with the ability of the hardware programming in an FPGA, on a single device. To communicate between the ARM processor and the FPGA, AXI-Bus interface is implemented. The ARM processor executes software in order to send inputs from the PC to the ION and receive results from the ION and show them on the screen on the PC. To verify the ION in the FPGA, software is implemented and the software outputs are compared with the result of SystemC testbench reference model.