Dead Time Control Circuit in Monolithic GaN Class D Audio Amplifier

Master thesis (2023)

Authors

J. Pan Electrical Engineering, Mathematics and Computer Science

Contributors

Q. Fan Electronic Components, Technology and Materials - EEMCS (supervisor 1)
P.J. French Bio-Electronics - EEMCS (supervisor 2)
Marco Berkhout Goodix Technology (supervisor 2)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Jing Pan
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Published Date

13-10-2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

GaN transistors have advantages over conventional Si MOSFETs, such as lower on-resistance, lower parasitic capacitance, higher break-down voltage, etc. However, due to the lack of the body diode, when GaN transistors conduct reverse current during dead time, the source-drain voltage (VSD) can be very large (up to 4-5 V, depending on the output current). High reverse conduction voltage leads to large power loss during dead time for the GaN class D amplifier. In this project, a dead time control circuit is proposed. With the dead time control circuit, the dead time can be reduced from a large default value to around 5 ns. The output power of the class D amplifier can be improved, and the third-order harmonic distortion can also be improved by 5-10 dB for different corners and temperatures.