Digitally Intensive Frequency Synthesis and Modulation Exploiting a Time-mode Arithmetic Unit

Abstract

Reducing power consumption is becoming increasingly important for the sustainability of the communication industry because it is expected to consume a significant portion of the global electricity in the face of the exponentially increasing demands on the volume and rate of data transmission. As the scope narrows to the individual wireless device level, the reduced power consumption helps to extend the lifetime of battery-powered devices, thereby leading to improved user experience and enabling the development of innovative applications. The quest for the lower power consumption will profoundly shape the wireless transceiver design, i.e., each critical block in the system should constantly reduce its drained power without sacrificing the performance. With this background, the thesis focuses on the phase-locked loops (PLL) that generate RF clocks for wireless transceivers, and develops low-power techniques suppressing the fractional-spur levels when the PLL generates unmodulated carrier, and the phase modulation (PM) error when the PLL additionally serves as a two-point modulator...