Structured design of an external NMOS based linear voltage regulator for automotive applications

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Abstract

The electronization of automobiles is considered to be a revolution in automotive technology development progress. System level integrated circuits are needed to simplify the automotive electronics design and increase the reliability of automobiles. In this thesis, a prototype of a linear voltage regulator is designed for system level integration. Instead of a conventional Internal PMOS or NMOS linear regulator topology, an external NMOS transistor produced by NXP is chosen as the pass device on considerations of certain commercial application. The parasitic inductance and capacitors of PCB traces and packaging are both modeled and calculated. The requirement differences of internal and external NMOS linear regulators are compared. This external NMOS transistor complicates the high-frequency design of this voltage regulator. The development of frequency compensation strategies as well as their implementation is the core of this work. Based on transistor models made by the author and the Root-Locus analysis method, the effectiveness of conceptual active compensation is examined in this thesis, and a passive frequency compensation scheme is proposed. This proposed scheme is not only able to accommodate the wide variation of load capacitor (470nF to 47μF) and the wide variation of load current (0 to 250mA) but also able to be compatible with the external NMOS. The effectiveness of passive frequency compensation is examined by both Root Locus analysis and transistor level simulation. The over-current protection of the NMOS linear regulator is also designed, which is realized by applying another current regulation loop to the voltage regulator. This voltage regulator is able to maintain a constant output current around 400mA in over-current protection scenario. The regulator quiescent current is 10μA, the output voltage accuracy is ±2%. At the end of this thesis, the performance aspects are discussed and analyzed, and the influence of parasitic PCB trace and packaging is examined.