On-chip SPAD array with IO designed for quantum sensing

On-chip SPAD array with IO designed for quantum sensing

van Rijs, Samantha (TU Delft Electrical Engineering, Mathematics and Computer Science)
Westenbrink, Dagmar (TU Delft Electrical Engineering, Mathematics and Computer Science)
Visser, Lars (TU Delft Electrical Engineering, Mathematics and Computer Science)

Ishihara, R. (mentor)
Varveris, I. (mentor)
van der Veen, A.J. (graduation committee)
Krasnov, O.A. (graduation committee)

Delft University of Technology

Electrical Engineering

2023-06-28

In this Bachelor graduation project, a 16x16 Single Photon Avalanche Diode (SPAD) array is designed in 40nm TSMC CMOS for diamond single Nitrogen Vacancy center array readout. It includes an active quenching and recharge circuit (AQC), a hold-off circuit for controllable dead-time and IO electronics for off-chip communication. The chip is part of a proposed high sensitivity magnetometer based on single NV center readout with a focus on detecting cancer in biological samples. From the Quantum Integration Technology (QIT) lab, pre-designed SPADs were received to be implemented into the design together with SPAD quenching, recharge and input-output controller electronics. A SPAD model is adapted from literature for simulations of the electric behaviour of the electronics. We present a design and implementation of the Active Quenching Circuit (AQC), a design and implementation of the recharge and hold-off circuits, Input-Output (IO) interface design and implementation and the final top-level implementation ready for the next tape out. Post-layout simulations show negligible speed slowdown and distortion. The AQC has a 12ns quenching time and a 1ns recharge time, leading to a theoretical maximum count rate of 76Mc/s. The hold-off circuit has a tunable dead-time for afterpulsing reduction and 16, 16 bit parallel-in-serial-out (PISO) modules allow per-row readout of the array. The electronics are co-located with the SPADs and pixel pitch is 24𝜇m. The final chip design meets the single NV fluorescence count rate requirement of above 3 Mc/s, the 1.1x1.1 𝑚𝑚2 area requirement, the 32-pin IO requirement, the 16x16 SPAD pixel requirement and, steps have been taken to ensure acceptable crosstalk levels in the array. Finally, the SPAD array chip is designed to run on a 1GHz clock. It should interface with an FPGA that configures the hold-off circuit and reads out the SPAD status bits.

SPAD
NV centers
Single-Photon Avalanche Diode Array

http://resolver.tudelft.nl/uuid:d6644989-1269-45b0-bed1-70e7640c4c00

Student theses

bachelor thesis

© 2023 Samantha van Rijs, Dagmar Westenbrink, Lars Visser