A power-efficient Delta-Sigma ADC with a passive input stage for audio applications

Master thesis (2022)

Authors

V. Pecanins Martínez Electrical Engineering, Mathematics and Computer Science

Contributors

Kofi A.A. Makinwa Microelectronics (mentor)
K.A.A. Makinwa Microelectronics (mentor)
Faculty
Electrical Engineering, Mathematics and Computer Science, Electrical Engineering, Mathematics and Computer Science
Copyright: © 2022 Victor Pecanins Martínez
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Published Date

26-09-2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

Several techniques have been proposed to reduce the swing at the input stage of a CTDSM. One of these is using a simple passive RC input stage. In prior works, this increased in-band quantization noise. In this paper, we use positive feedback to realize complex-conjugate poles with a passive input stage, obtaining the same noise-shaping as an Active-RC-based loop filter. The prototype 16nm chip achieves a peak SNDR=97.6dB and DR=99.5dB with an SNDR FOM=181.2dB and DR FOM=183.0dB in 20kHz bandwidth.

Files

VPM_Thesis_2022.pdf
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