A 9-bit 33MHz Hybrid SAR Single-slope ADC

Master thesis (2015)

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Programme
Micro-electronics (EEMCS) (TU Delft)
Copyright: © 2015 Hu, W.
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Published Date

16-12-2015

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Programme

Micro-electronics

Abstract

In this work a 9-bit, 33MHz hybrid SAR single-slope ADC for element-level digitization in 2D ultrasound transducer arrays is presented. This hybrid architecture consists of a 5-bit SAR ADC followed by a 4-bit single-slope ADC. In the comparator design, the dynamic comparator and the continuous-time comparator for the SAR and single-slope conversion, respectively, are combined together with a shared preamplifier. The simulated ENOB is 8.96 bit, the power consumption is 800uW, the estimated area is 0.015mm2 and the achieved FoM is 48.7fJ/conv-step.