Characterization and modeling of mismatch in Cryo-CMOS

Characterization and modeling of mismatch in Cryo-CMOS

't Hart, P.A. (TU Delft OLD QCD/Charbon Lab)
Babaie, M. (TU Delft Electronics)
Charbon-Iwasaki-Charbon, E. (Swiss Federal Institute of Technology)
Vladimirescu, A. (TU Delft OLD QCD/Charbon Lab; University of California; Institut Supérieur d’Electronique de Paris,)
Sebastiano, F. (TU Delft (OLD)Applied Quantum Architectures)

2020

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both absolute value and variability as a function of temperature and device size were investigated. It is shown that the Pelgrom scaling law is valid also at 4.2 K and that the simplified Croon model is able to accurately predict drain-current mismatch from moderate to strong inversion over the entire temperature range. Additionally, the characterization of linear device arrays shows exacerbated edge-effects at extremely low temperatures, thus requiring the addition of dummy devices at the array boundary. The result of this study is the first model capable of predicting mismatch over a wide range of operating regions and temperatures.

Cryo-CMOS
Cryogenics
cryogenics
Logic gates
Mismatch
modeling
MOSFETs
quantum computing.
Qubit
stress
Temperature distribution
Temperature sensors

http://resolver.tudelft.nl/uuid:d9f4e392-ed7c-4bab-a0c8-00e7a6d55524

https://doi.org/10.1109/JEDS.2020.2976546

IEEE Journal of the Electron Devices Society, 8 (1), 263-273

Institutional Repository

journal article

© 2020 P.A. 't Hart, M. Babaie, E. Charbon-Iwasaki-Charbon, A. Vladimirescu, F. Sebastiano