Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

Conference paper (2018)

Authors

F. Augusto da Silva Cadence Design Systems
Ahmet Cagri Bagbaba Cadence Design Systems
Said Hamdioui Quantum & Computer Engineering
S. Hamdioui Quantum & Computer Engineering
Christian Sauer Cadence Design Systems
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2018 F. Augusto da Silva, Ahmet Cagri Bagbaba, S. Hamdioui, Christian Sauer
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Published Date

2018

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

This work aims at an alternative method to verify the correctness of Fault Lists generated by fault simulators tools in context of safety verification. The lists generated by simulation tools are verified against lists from formal tools. The consistency evaluation between the lists supports the Tool Confidence Level (TCL) assessment, defined in the ISO26262. In addition, formal tools have the potential of performing optimization in Fault Lists by annotation of the expected behavior of the design under fault. Our work demonstrates the feasibility of using Formal Methods to verify and optimize the fault list from simulators. Results indicate an average reduction of 29.5% on the number of faults to be simulated and demonstrate that it is possible to achieve TCL by verification of the fault lists.

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