Hardware Acceleration of Monte-Carlo Integration in Finance

Abstract

This thesis describes FPGA-accelerated Monte-Carlo integration using adaptive stratified sampling. Monte-Carlo integration can be used to determine the value of integrals that have no closed form solution. In this work, the FPGA-accelerated design is used to determine the price of different types of financial options. The considered options are a basket option, an Asian option and a barrier option. Stratified sampling is implemented with the recursive general purpose algorithm MISER. First, a parallel software implementation of MISER is developed. Next, the integrand independent part of the software is moved into reconfigurable hardware. Finally, the different options are priced in FPGAs by developing hardware implementations of the integrand for each option. The integrands are compiled into a deep pipeline, producing one function evaluation per cycle at 150 MHz. The FPGA-accelerated design requires up to 4200 times less execution time to achieve the same accuracy as a software implementation using the GSL library running on an Intel i7-4770 CPU at 3,40 GHz.