Dynamic cache configuration for the ρ-VEX platform

Abstract

The ρ-VEX is a processor designed at the Computer Engineering lab at TU Delft to be reconfigurable at runtime, resulting in a processor that can combine or separate instruction lanes according to the program requirements. The current cache for the ρ-VEX processor is direct mapped and always identical to the instruction group configuration. This is limited and not flexible, and a more flexible cache that can be reconfigured at runtime is desirable. This thesis introduces a more flexible cache, which is achieved by replacing the replacement policy with a more flexible variant, as well as adding an extra cache tree. The addition of the second cache tree allows for a more flexible cache size assignment, as either cache blocks of the small or the larger cache tree can be assigned to a specific instruction group. The assignments of the cache blocks can be reconfigured during runtime. The replacement policy is replaced by round robin and (pseudo) LRU, giving the required flexibility, as well as decreasing cache misses, which results in better overall performance for the $ρ$-VEX. Round Robin reduces the runtime when the application heavily uses the caches by 11.7%, but increases the runtime when the application has a low cache utilization. LRU always reduces the application runtime, and reduces the run times of cache heavy applications by about 13%.