Design Study on the Switched and Linear Operation of Broadband CMOS Class-E Power Amplifiers

Abstract

This research work aims to gain understanding of the power amplifier (PA) operating as a linear PA under low power drive conditions and as a switch-mode PA in high power drive conditions both with the same Class-E load. Two approaches were taken here. Firstly, an analytical approach was developed to investigate the switching operation of conventional Class-E amplifier. The model used in the analytical approach takes into account the non-ideal switch resistance, finite dc-feed inductance, finite loaded quality factor, and arbitrary switch duty-cycle. This approach presents an accurate closed-form expression for modeling Class-E power amplifier. Using this approach, the frequency response of conventional Class-E power amplifier was studied in detail and the impact of the loaded quality factor and finite dc-feed inductance on the broadband performance was analyzed. It shows that the Class-E PA with conventional load network cannot provide stable output power, efficiency, and reliable operating voltage conditions across a broad frequency band (Bandwidth > 40%). In addition, study of the load impedance of the amplifier indicates that the Class-E PA is sensitive to the load phase angle at fundamental frequency. In the second approach, a purely linear voltage-control current source was constructed numerically as a way to represent the transistor. Based upon that model, the influence of non-ideal drive signal on the switching operation was studied. It shows that the power amplifier with finite dc-feed inductance is tolerant to a non-ideal drive signal. For the rise and fall times of 25%T, only 5% drop in drain efficiency was found for the optimum finite dc-feed inductance. The performance of that model in linear operation was also investigated. The results agree with the classical theory for linear power amplifiers. The linearity (intermodulation distortion and 1dB compression point) was analyzed by using a realistic transistor model (an extended drain NMOS). It shows that the Class-B biased PA with finite dc-feed inductance can provide not only similar IMD3 feature as the optimum Class-AB biased PA with RF choke does, but also high efficiency simultaneously. Based upon this device, a systematic design process was applied to implement a broadband high efficiency Class-E PA. The PCB for this broadband high efficiency Class-E PA was fabricated. Good agreement was found between the simulation and measurement. The measurements indicated that the PA achieves a drain efficiency >67% and a PAE >52% with a Pout >30dBm from 560-1050MHz, where the output power variation is within 1.0dB and efficiency variation is within 13%. The highest efficiency is observed at 700MHz from a 5.0V supply with peak drain efficiency of 77% and peak PAE of 65% at 31dBm output power and 17dB power gain. When using dynamic supply modulation, the PA achieves a PAE of 40% and a drain efficiency of 60% at 10dB power back-off across the frequency band 500MHz to 1100MHz.