Low Power Evaluation for Arbitration and MPSoC

Abstract

This thesis presents a power analysis for various arbitration schemes. We chose variations on the round-robin and time-division multiplexing schemes as our arbiter configurations. The arbiters were implemented with 90 nm low-power standard cell libraries from TSMC, and gate-level power extraction was performed. Clock-gating was optionally introduced during synthesis. We then contrasted the power dissipation for the different arbiters and showed that no single arbitration scheme performs well in terms of power dissipation under all load conditions. We also analyzed why the power dissipation curve of a round-robin arbiter shows a point of maximum inflection. This thesis implements also a multiprocessor system-on-chip design. Such designs can offer significant power savings over traditional uniprocessor designs. We analyzed the power of such a system, and showed how it can be constructed in both hardware and software.