Reducing Switching Artifacts in Chopper Amplifiers

Abstract

This thesis describes the theory, design, and implementation of chopper operational amplifiers (op-amps) in CMOS integrated circuits (ICs). The chopping technique periodically corrects DC errors of such op-amps, so that low 1/f noise and stable, microvolt-level offset can be achieved. However, chopping causes switching artifacts at the amplifier’s output, e.g. up-modulated ripple and glitches, which are usually attenuated by low-pass filtering. Therefore, chopper op-amps have mainly been limited to low frequency applications. In this thesis, advanced circuit techniques are proposed to attenuate such switching artifacts without decreasing the usable signal bandwidth, thus enabling the use of chopper op-amps in a broader range of applications. Three chopper op-amps are designed, fabricated, and measured, so that the proposed techniques can be evaluated and compared with those of the other state-of-the-art designs. In the first design, a ripple reduction technique called auto-correction feedback (ACFB) is proposed, which continuously detects and cancels the ripple in a power and area efficient manner, so that the overall op-amp only draws 13µA from a 1.8V to 5.5V supply and occupies a 0.64mm2 die area. In the second design, an adaptive clock boosting technique for input switches is proposed, so that their charge injection mismatch is minimized and independent of changes in the supply and input common-mode voltages. As a result, 0.5µV maximum offset and 5.6nV/√Hz noise PSD are achieved over the op-amp’s entire rail-to-rail input common-mode range. In the third design, six parallel input transconductors are driven by interleaved 800kHz clocks, which pushes the PSD peak up to 4.8MHz. Furthermore, an on-chip charge mismatch compensation circuit is employed to reduce the maximum input bias current from 1.5nA down to 150pA in post-production trimming.