Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors

Abstract

In this thesis we consider the application of multi-cores in safety critical real-time systems, especially avionics. In our literature study we extract two major challenges. Firstly the unpredictability that comes from the concurrent access of shared resources (especially the on-chip interconnect) must be dealt with. To address this we propose to extend the concept of partitioning which provides fault containment, in combination with resource reservation at design time. The second challenge is to optimize the hardware usage without compromising on the determinism inherent to static mapping and scheduling. We propose mode-based mapping to deal with this, which allows to switch between multiple static schemes. We capture these concepts in a simple formal model. Mode-based mapping is enabled by task migration. The transfer time of tasks must be bounded, which requires guarantees on the Quality-of-Service (QoS) offered by the interconnect. Modern multi-cores feature Networks-on-Chip (NoC), which are packet-switching interconnects consisting of links and routers. Key to deterministic behaviour of NoCs this is avoiding contention, this can be achieved with flow control and buffering strategies based on resource reservation. We propose the use of transient modes to control the changes between the different modes in a NoC. To evaluate different transfer methods we conducted a number of experiments on a 64-core processor that features a NoC. The experiments show that both data prefetching from the shared cache and the programmer accessible networks are suitable for deterministic task transfer. The former is twice as fast but the number and size of shared data objects must be limited because timing analysis of large coherent shared caches is not feasible. For all methods the maximum deviation from the mean values is constant (0,4 us), and the standard deviation is under 1/2 % of the total transfer time. This shows that these methods are deterministic and that a tight bound on the transfer time can be determined. We conclude that private caches and scratchpads are suitable memory architectures for real-time systems, which can be supported by message passing and explicit communication through small shared memory regions. Mapping traffic at design time avoids contention, and isolation of traffic at the transfer level offers additional fault-tolerance. We propose a number of improvements for the transfer methods considered in our experiments that will enable guarantees on QoS. Our experiments confirm the feasibility of the proposed concepts.