A 12-bit 500MS/s Pipeline Split-ADC

Master thesis (2010)

Authors

Contributors

K. Bult (mentor)
J.R. Long (mentor)
Department
Microelectronics & Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2010 Sehgal, R.
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Published Date

03-09-2010

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics & Computer Engineering

Abstract

"Split-ADC" calibration is a recently proposed digital background calibration architecture. It requires a much lower number of cycles to calibrate the ADC errors due to its deterministic nature, without placing any additional analog complexity. While new error estimation techniques are being explored using this architecture through simulations, a hardware platform flexible in terms of performance and power consumption is much more desirable. A 12-bit, 500MS/s pipeline "Split-ADC" is designed in TSMC 65nm CMOS. The stage amplifiers of the pipeline ADC are designed to be power scalable so that their settling time varies linearly over a wide range of bias current. A higher power efficiency is achieved in the ADC by using the current-mirror opamp topology in the MDACs operating at 1V supply, and by removing the sample-and-hold amplifier. The overall pipeline ADC displays a peak SNDR of 66dB at a sampling frequency of 312.5 MS/s, with the analog core of each half-ADC consuming 77.3mW. This translates into a peak figure of merit of 0.3pJ/conversion for the designed split-ADC.