Analysis and Test Development for Parasitic Fails in Deep Sub-Micron Memory Devices

Abstract

Emerging technology trends are gravitating towards extremely high levels of integration at the package and chip levels, and use of deeply scaled technology in nanometer, approaching 10nm CMOS. Challenges will arise due to the ability to design complex systems such as robots that encompass sensors, transducers, communications systems and processors, all of which require memory devices, and are required to be fault-free, and exhibit fault-tolerance, reliability and survivability characteristics. A key area of challenge is in memory testing, since deep scaling and smaller dimensions of semiconductor cell area will exacerbate the presence of complex defects and can induce effects, such as parasitic effects, which necessitate fails in memory devices. In this thesis, parasitic effects induced by spot defects in memory devices have been evaluated. The thesis presents the analysis, evaluation, validation and test remedies for parasitic fails in deep sub-micron memories. On the one hand, it presents analysis for parasitic bit line coupling effects, and the impact of bit line coupling effect on the static random access memory (SRAM) faulty behavior. Thereafter, it determines both the necessary and sufficient detection conditions for memory fault models, and demonstrates the limitations of existing industrial memory tests to adequately detect faults in the presence of bit line coupling. In addition, the thesis presents a systematic approach for test development and optimization, and new memory tests - March SSSc an optimal test that detects all single-cell static faults, and March m-MSS and March BLC that detect all two-cell static faults, in the presence and absence of bit line coupling. On the other hand, this thesis also presents the analysis, evaluation, validation and test remedies for parasitic memory effect in SRAMs. The work presents the impact of the parasitic memory effect on the detection of static faults, and clearly shows that fault detection is influenced by the presence of parasitic node components and not the resistive defect alone; something that must be considered in generating effective memory tests. In addition, the thesis presents the detection conditions and a new memory tests, March SME that targets and detects single-cell static faults, in the presence of the parasitic memory effect.