Structured Electronic Design of High-Pass ∆Σ Converters

Abstract

With the bandwidth of the ECG signal extending from sub-Hz to 200 Hz, a major challenge for an ECG readout system lies in implementing the high-pass (HP) cut-off frequency as this translates into the realization of large time constants on-chip.Although techniques such as those based on the use of pseudo-resistors to obtain very large time constants exist, they are heavily limited in both linearity and accuracy, which clearly dictates the need for alternative structures. A structured electronic design approach based on state-space forms is proposed to develop HP ∆Σ converters targeting high accuracy of the HP cut-off frequency. Based on transfer function calculations, the various specific HP ∆Σ topologies namely, biquad, observable and controllable canonical and orthonormal HP ∆Σ, can be made to satisfy the desired HP signal transfer with 2nd order noise-shaping. In order to establish the noise contributions of the integrators, intermediate transfer functions, viz., from the system input to the integrator outputs, and from the integrator inputs to the system output, respectively are mathematically derived and evaluated. The evaluation of the intermediate transfer functions show that the orthonormal topology is better than the observable canonical HP ∆Σ topology in terms of noise. Simulations conducted in MATLAB confirm the noise behaviour of the integrators and show that, apart from the first integrator, the HP integrator significantly contributes to the total noise. Secondly, the noise and the harmonics at higher frequencies from the HP integrator are low-pass filtered. A 2nd order orthonormal HP ∆Σ modulator with a sampling frequency of 128 kHz for a bandwidth of 1-200 Hz to be implemented in 0.18 um AMS technology achieves a resolution of 12-bits at the HP cut-off frequency of 1 Hz which is a major improvement over pseudo-resistors at the cost of higher area and power consumption. A robust, area-efficient and parasitic insensitive large time constant switched-capacitor Nagaraj integrator leads to a HP cut-off frequency realization determined solely by the ratio of capacitors with an accuracy upto 1%. In conclusion, HP ∆Σ topologies that can be used to realize very large time constants with high linearity and accuracy which shows a major improvement over the conventionally used topologies that employ pseudo-resistors are proposed.