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Special Session: STT-MRAMs: Technology, Design and Test
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
Protecting IoT Devices through a Hardware-driven Memory Verification
Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron
Improving the Detection of Undefined State Faults in FinFET SRAMs
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
LightRoAD: Lightweight Rowhammer Attack Detector
Spin wave based full adder
Intermittent Undefined State Fault in RRAMs
Achieving Wave Pipelining in Spin Wave Technology
Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs
Fan-out of 2 Triangle Shape Spin Wave Logic Gates
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture
Modeling Soft-Error Reliability Under Variability
Spin Wave Based 4-2 Compressor
Deterministic and Statistical Strategies to Protect ANNs against Fault Injection Attacks
Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects
The Power of Computation-in-Memory Based on Memristive Devices
Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level
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