Dynamic cache configuration for the ρ-VEX platform

The ρ-VEX is a processor designed at the Computer Engineering lab at TU Delft to be reconfigurable at runtime, resulting in a processor that can combine or separate instruction lanes according to the program requirements. The current cache for the ρ-VEX processor is direct mapped and always identical to the instruction group configuration. This...

Dynamic Hardware Binary Translator for ρ-VEX

The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor...

Fingerprint Verification on the VEX Processor

The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...