Tydi-lang: a language for typed streaming hardware: A manual for future Tydi-lang compiler developers

Transferring composite data structures with variable-length fields often requires designing non-trivial protocols that are not compatible between hardware designs. When each project designs its own data format and protocols the ability to collaborate between hardware developers is diminished, which is an issue especially in the open-source...

Integration of a convolutional neural network for speech-to-text recognition in an FPGA compiler flow

Deep Neural Network (DNNs) have increased significantly in size over the past decade. Partly due to this, the accuracy of DNNs in image classification and speech recognition tasks has increased as well. This enables a great potential for such models to be applied in real-world applications. However, due to their size, the compute and power...

Visualization tools: for the OpenQL compiler

The rapid progress quantum devices have made in recent years has led to the need for systems that bridge the gap between quantum algorithms and quantum hardware. To this purpose different full-stack quantum programming platforms have been developed, providing high level languages for expressing quantum algorithms and providing compilers for...

Compiling with Command Trees

Compilers translate high-level source code into low-level machine code. To represent source code a compiler uses a language called the intermediate representation (IR). An IR for the compilation of functional languages is continuation-passing style (CPS). It provides convenient abstractions for both data flow and control flow. However, CPS...

Hardware enforced fine grained data labeling on RISC-V using RUST

Software bugs in many different variants can potentially leak sensitive data to an attacker. Implementing a separation mechanism for security domains can prevent incorrect or malicious code to leak sensitive data from one security domain to another. This work presents a separation mechanism based on labeling security domains with a label in...

Automated FPGA Hardware Synthesis for High-Throughput Big Data Filtering and Transformation: An SQL query transpiler targeting Vivado HLS C++ tools for high-level stream transformation and filtering on FPGAs using Apache Arrow.

Despite its advantages in performance and control, hardware design is mainly bottlenecked by high design complexity and long development time. This thesis explores the use of domain specific languages for high-level synthesis (HLS) of hardware data filters and transformations.<br/>The main goal of this thesis’ prototype is automating the...

The Static Semantics of the Green-Marl Graph Analysis Language: Formal Specification, Declarative Implementation and Integration with a Compiler Back-end

Green-Marl is a domain specific language for efficient graph analysis. In this thesis, we define the formal static semantics of the language and provide an implementation in the Spoofax language workbench. The type system of Green-Marl includes limited forms of name-dependent types, overloading, parametric polymorphism, and inference. We give a...

A Generative Approach for Data Synchronization between Web and Mobile Applications

Mobile developement is a relatively new and popular domain for applications. An increasing amount of web applications are releasing a mobile variant of their application, which requires sharing of data. Currently, the creation of a mobile version can be done in two ways: a specialized web UI for mobile devices, which lacks good abstractions for...

A Generic and Automatic Test Strategy for Compiler Testing

Domain-specific Languages (DSLs) are languages specifically tailored for an application or expert domain. These can be implemented as compilers, which check the correctness of an input program and translates it to a target language. Manual testing of compilers is a time consuming and labor intensive task. This motivates the development of...

Iterative Instruction Scheduling for a VLIW Processor

Instruction scheduling aims to reorder instructions in such a way that it covers the delay between an instruction and its dependent successor(s). As a result, the length of schedules are shortened while the processor utilisation increases. This is accomplished by exploiting Instruction Level Parallelism (ILP). The rearrangements made by...

Porting GCC to a Clustered VLIW Processor

A clustered architecture is a viable design choice when aiming to increase the performance of a VLIW processor while avoiding the hardware complexity and increased access times associated with a centralized register file. However, this places additional responsibility on the compiler: the production of an efficient cluster assignment. In this...

Compile time aanalysis for hardware transactional memory architectures

Transactional Memory is a parallel programming paradigm in which tasks are executed, in forms of transactions, concurrently by different resources in a system and resolve conflicts between them at run-time. Conflicts, caused by data dependencies, result in aborts and restarts of transactions, thus, degrading the performance of the system. In...

A solution to misaligned data access in a vectorizing compiler framework

Vectorizing code for short vector architectures as employed by today’s multimedia extensions comes with a number of issues. The responsibilities of these issues are moved to the compiler in order to keep hardware simple. One of those issues is memory-alignment, which requires the compiler to guarantee loading and storing vectors at aligned...

VHDL to SystemC: The Design of a Translator

VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to an equivalent model in SystemC. A system in SystemC can be needed for modeling a system with a software part, for a faster simulation, or because some tools only support SystemC. This thesis presents a...

SPIN's Promela to Java Compiler: With help from Stratego

In model checking a formal model of a software system is constructed. That model is verified against a set of properties expressed in some logic. Once a model has been created and verified, it is still necessary to write the application itself completely by hand. No tools have yet been developed that can automatically create a system or...

Een front-end compiler voor SDL-PR

Met behulp van het GAG-systeem is een front-end compiler voor SDL-PR gegenereerd. In dit verslag zal de gevolgde aanpak worden toegelicht en de opgedane ervaring worden geevalueerd.