WARio: efficient code generation for intermittent computing

Intermittently operating embedded computing platforms powered by energy harvesting require software frameworks to protect from errors caused by Write After Read (WAR) dependencies. A powerful method of code protection for systems with non-volatile main memory utilizes compiler analysis to insert a checkpoint inside each WAR violation in the...

Automatic Hardware Generation for Reconfigurable Architectures

Reconfigurable Architectures (RA) have been gaining popularity rapidly in the last decade for two reasons. First, processor clock frequencies reached threshold values past which power dissipation becomes a very difficult problem to solve. As a consequence, alternatives were sought to keep improving the system performance. Second, because Field...

Porting GCC to a Clustered VLIW Processor

A clustered architecture is a viable design choice when aiming to increase the performance of a VLIW processor while avoiding the hardware complexity and increased access times associated with a centralized register file. However, this places additional responsibility on the compiler: the production of an efficient cluster assignment. In this...