The delamination process of the dross build-up structure on submerged hardware in Zn-Al and Zn-Mg-Al baths: An empirical study

Hot-dip galvanizing is a well-known process to increase the corrosion resistance of steel. As a by-product dross is formed in the Zn-bath. The dross particles are composed of Fe, Al and Zn in the form of Fe2Al5Znx and interact with the hardware that is submerged in the Zn-bath and eventually accumulate on the surface of the hardware. This...

Efficient C₂-weighting for image warping

Handle-driven image warping based on linear blending is widely used in many applications because of its merits on intuitiveness, efficiency, and ease of implementation. In this paper, we develop a method to compute high-quality weights within a closed domain for image warping. The property of C₂ continuity in weights is guaranteed...

Automatic Hardware Generation for Reconfigurable Architectures

Reconfigurable Architectures (RA) have been gaining popularity rapidly in the last decade for two reasons. First, processor clock frequencies reached threshold values past which power dissipation becomes a very difficult problem to solve. As a consequence, alternatives were sought to keep improving the system performance. Second, because Field...

Low-Cost Smith-Waterman Acceleration

Due to advancing technology, genetic sequencing has become cheaper over the years. This has caused the demand for computational power to grow even faster than Moore's law. To remedy this problem, we analyzed low-cost hardware solutions to parallelize the computational part of the genetic sequencing. We proposed a novel method for calculating the...

Compile time aanalysis for hardware transactional memory architectures

Transactional Memory is a parallel programming paradigm in which tasks are executed, in forms of transactions, concurrently by different resources in a system and resolve conflicts between them at run-time. Conflicts, caused by data dependencies, result in aborts and restarts of transactions, thus, degrading the performance of the system. In...

Evaluation Methodology and Systematic Selection of Microcontrollers for Delfi-n3Xt Nanosatellite

Generic and Orthogonal March Element based Memory BIST Engine

A Memory BIST architecture and implementation based on the novel concept of Generic and Orthogonal March Element