Designing Asynchronous Gate Library with new System Level Trade-offs

This dissertation describes an approach to building a self-timed asynchronous pulse-mode serial link circuit. Unlike asynchronous handshake circuits or synchronous circuits, this design style does not require any feedback control blocks, which can increase latency, or any clock recovery circuits, which can increase energy consumption and...

A Highly Concurrent, Memory-Efficient AER Architecture for Neuro-Synaptic Spike Routing

One of the challenges of neuromorphic computing is efficiently routing spikes from neurons to their connected synapses. The aim of this thesis is to design a spike-routing architecture for flexible connections on single-chip neuromorphic systems. A model for estimating area, power consumption, memory, spike latency and link utilisation for...