A High Speed DAC Architecture for Continuous Time Pipeline ADC

This thesis provides an investigation of the architecture and the design of the coarse DACs in continuous time pipeline (CTP) ADC to achieve high SFDR performance within a large bandwidth at sampling frequency of 4.8 GHz in TSMC 28nm technology.<br style="box-sizing: border-box"/> Mismatch errors of the coarse DACs in CTP ADC are very...

A 10 bit 5 MS/s column SAR ADC with digital error correction for CMOS image sensors

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence...

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh...