A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to...

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ΔΣ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still...