A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From -45 °C to 85 °C

This article presents a 16-MHz RC frequency reference implemented in a standard 180-nm CMOS process. It consists of a frequency-locked loop (FLL) in which the output frequency of a digitally controlled oscillator (DCO) is locked to the frequency-phase characteristic of a Wien bridge RC filter. Since it is made from on-chip resistors and...

A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail...

A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to...

A CMOS Dual- RC Frequency Reference With ±200-ppm Inaccuracy From -45 °C to 85 °C

This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven...

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal...

Numerical Model of an Injection-Locked Wideband Frequency Modulator for Polar Transmitters

We present a numerical model of a wideband injection-locked frequency modulator used in a polar transmitter for 3G cellular radio application. At the heart of the system is a self-injection-locked oscillator with a programmable linear tuning range of up to 200 MHz at 4-GHz oscillation frequency. The oscillator is injection locked to a time...

An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

In this paper, we apply various area reduction techniques on an inductor–capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact...

A Bluetooth Low-Energy Transceiver with 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F₂...

Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division

In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection...