Throughput and Power optimization of the Range Trie design for IP lookups

This thesis aims to improve the Range Trie design on throughput and power consumption. The Range Trie is an SRAM based design that offers competitive performance and is scalable enough to withstand current and future expectations, especially the transition from IPv4 to IPv6. This thesis is exploring the possibilities in partitioning the last and...

Design and Prototype of the Range-Trie IP: Lookup in the HTX reconfigurable platform

In this thesis the design and FPGA implementation of the Range Trie with Longest Prefix Match and updates is completed and prototyped in an HTX reconfigurable system. The design and its implementation is an example of hardware/software co-design and supports hardware functions controlled by software using system calls. In the case of the Range...

Design and Implementation of a Range Trie for Address Lookup

The rapid growth of internet traffic and the eminent shift from IPv4 to IPv6 addresses indicated the need for an efficient address lookup method that can keep pace with the ever-increasing throughput demands. As current address lookup solutions tend to become the bottleneck in internet routing, the efficient Range Trie address lookup method was...