Experimental and Industrial Evaluation of Variability Resilient Schemes

As semiconductor devices shrink further, the effects of process variation become more and more pronounced. They negatively impact the speed and power consumption of Integrated Circuits (ICs). Traditionally, a worst-case based design methodology is used to compensate for their potential impact. For modern technology this method means an increased...

A 4 X 4 X 416 digital SiPM array with 192 TDCs for multiple high-resolution timestamp acquisition

We present a 4 X 4 array of digital silicon photomultipliers (D-SiPMs) capable of timestamping up to 48 photons per D-SiPM and we show the advantage of generating multiple timestamps in the context of positron emission tomography (PET). The D-SiPMs have a pitch of 800 ?m and comprise 416 pixels each; the timing resolution achieved by the SiPMs...

90 nm VLSI Design of an 8-bits Microcontroller

Integrated Circuit (IC) design complexity has increased radically since the first "hand-made" designs in the late 50s, with a few transistors. Nowadays, Very Large Scale Integration (VLSI) designs contains hundreds thousand, million or even billion transistors and not only the experience of the designer, but also Electronic Design Automation ...

Hybrid models for parasitic capacitances in advanced VLSI circuits

Morphological image processing: Architecture and VLSI design

Hierarchical verification of VLSI artwork

An efficient data structure and algorithm for VLSI artwork verification