Iterative Instruction Scheduling for a VLIW Processor

Instruction scheduling aims to reorder instructions in such a way that it covers the delay between an instruction and its dependent successor(s). As a result, the length of schedules are shortened while the processor utilisation increases. This is accomplished by exploiting Instruction Level Parallelism (ILP). The rearrangements made by...

Compiler Strategies for Transport Triggered Architectures

Compiler technology plays an important role to enhance the performance of modern microprocessors. In this thesis, compiler techniques and strategies are described to enhance the performance of microprocessors based on the Transport Triggered Architecture. The interaction between two important phases in a compiler, instruction scheduling and...