Liu, Bangan (author), Zhang, Yuncheng (author), Qiu, Junjun (author), Ngo, Huy Cu (author), Deng, Wei (author), Nakata, Kengo (author), Yoshioka, Toru (author), Emmei, Jun (author), Pang, Jian (author), Someya, T. (author) In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To...
journal article 2021
