There are nowadays strong business and technical demands to integrate radio- frequency (RF) receivers (RX) into a complete system-on-chip (SoC) realized in scaled digital processes technology. As a consequence, the RF circuitry has to function well in face of reduced power supply ( V DD ) while the CMOS device threshold voltage ( V th ) stays almost constant. Therefore, a conventional or continuous-time (CT) approach could not be efficiently utilized to design and implement the SoC, whereas a discrete-time (DT) approach offers the advantage for RF building blocks to operate properly in a smaller headroom. Furthermore, in finer CMOS technologies, transit frequency ( f T ) increases while CT RF building blocks do not benefit except for low-noise amplifiers (LNA). However, the performance of DT RF building blocks improves because of the higher sampling frequency ( f s ), lower power supply, and sharper clock edges provided by technology scaling. Nowadays, most integrated RF receivers are zero-IF (ZIF) because of well- known advantages such as less complicated architecture and easy channel-selection integration. They require many external duplexers, surface acoustic wave (SAW) filters, and switches, typically one per band, to attenuate out-of-band (OB) blockers. However, there are many issues associated with ZIF receivers such as time-variant DC offsets, sensitivity to 1 /f (flicker) noise, large in-band LO leakage, and second- order nonlinearity. For solving those issues, high-performance cellular SAW-less ZIF receivers now require extensive calibration efforts. For example, an intensive input 2 nd -order intercept point (IIP2) calibration must be simultaneously operated in the background with DC offset and harmonic rejection (HR) calibrations. Also, this calibration is susceptible to many factors such as variations in power supply, process corner, temperature, RF blocker frequency, local oscillator (LO) frequency, LO power, and channel frequency. On the other hand, a superheterodyne architecture pushes the IF frequency much higher so that the aforementioned problems are eliminated. Despite the advantages, the superheterodyne radios have not been utilized in cellular receivers simply because of the difficulty with integration of a high quality (Q)-factor band-pass filter (BPF) for image rejection in CMOS using CT circuitry. In this thesis, a new class of filters, i.e., charge-sharing (CS), is discussed that is being invented and developed to be utilized in not only superheterodyne but also in ZIF receivers. The proposed filter not only filters OB-blockers but also rejects interferers at the harmonic of LO frequency which is an extraordinary advantage especially for SAW-less receivers when there is no external filtering prior to the receiver input. Using these techniques, for the first-time ever, the superheterodyne receiver is proposed that meets the specification for SAW-less receivers. Chapter 1 briefly provides an overview of the blocks inside conventional RF radio transceivers. It mentions that there is a tendency in RF transceivers to support many of the multi-mode/multi-band communication standards such as Fourth Generation (4G) cellular application, Bluetooth, and Wi-Fi in one SoC. Also, the organization of the thesis has been described in details in this chapter. Chapter 2 establishes a common background for this thesis. Furthermore, it provides the background information for different sampling modes of operation such as subsampling (1x), half-rate sampling (2x) and full-rate sampling (4x) together with their frequency translations. Also, the technical mathematic background related to nonlinearity is briefly consolidated in this chapter. Chapter 3 discusses the first implemented DT superheterodyne receiver that utilizes the full-rate (4x) sampling mode of operation to solve a number of issues related to previous DT receivers. Chapter 4 explores performance capabilities and limitations of the proposed CS-BPF. A complex quadrature charge-sharing technique is proposed to implement a CS-BPF with a programmable bandwidth. It operates at the full sampling rate (4x), which was described in Chapter 2. Also, the complete noise analysis of the proposed CS-BPF is investigated. Additionally, the CT model of the CS-BPF is presented, and the filtering characteristic of proposed model has excellent agreement with the simulation result of the DT circuit. Finally, the implemented chip is fabricated in 65 nm CMOS, and the measured results are compared with simulations. Chapter 5 explores the possibility of creating a high quality (Q)-factor BPF at a very high IF because the CS-BPF proposed in Chapter 4 does not provide adequate selectivity. As a result, a highly reconfigurable superheterodyne RX is proposed that employs a 3rd-order complex IQ CS-BPF for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The proposed RX is the first attempt to achieve high-Q factor BPF at a very high-IF without replicas and images. Furthermore, the chip is fabricated in 65 nm CMOS technology, and the simulated results are completely verified by the measured results. Chapter 6 proposes and demonstrates the first-ever fully integrated SAW-less superheterodyne receiver for 4G cellular applications. The low-power DT RX introduces various innovations that simultaneously improve noise and linearity performance: a highly linear wideband noise-canceling LNTA, a blocker-resilient octal CS-BPF, and a cascaded harmonic rejection circuitry. The chip is fabricated in 28 nm CMOS technology, the characteristics of the fabricated chip are extensively measured, and the results are compared with the simulations. Chapter 7 draws the conclusions of this thesis work and provides recommendations for future research.