As CMOS technology progresses to the 45nm generation and below, lots of changes are developed on material, process and structure, such as, metal gates, high-k gate dielectrics, increased mobility, low-k wiring dielectrics, and multiple layers of circuitry (3D) . These new changes provide performance improvements and economic benefit, however face challenges on gate leakage, short channel effect, power dissipation and the various (parasitic) phenomena influences the accuracy and efficiency of analog and digital design. Consequently, extraction and verification of the design under deep submicron level is a big challenge. The main objective of this project is to evaluate the capabilities of the SPACE layout to circuit extractor for extraction of the 45nm technology. Firstly, technology files for the 45nm virtual technology are developed based on the FreePDK 45nm hypothetical technology from Nangate 45nm Open Cell Library. After building the technology files successfully, several suitable examples are developed for testing the technology files and demonstrating the most important SPACE features. Moreover, SPACE and Calibre verification flows are also compared in this project. Finally, the trade-off between SPACE 2D and 3D interconnect capacitance extraction is discussed.