Objective. The advent of high-performance computing (HPC) in recent years has led to its increasing use in brain studies through computational models. The scale and complexity of such models are constantly increasing, leading to challenging computational requirements. Even though modern HPC platforms can often deal with such challenges, the vast diversity of the modeling field does not permit for a homogeneous acceleration platform to effectively address the complete array of modeling requirements. Approach. In this paper we propose and build BrainFrame, a heterogeneous acceleration platform that incorporates three distinct acceleration technologies, an Intel Xeon-Phi CPU, a NVidia GP-GPU and a Maxeler Dataflow Engine. The PyNN software framework is also integrated into the platform. As a challenging proof of concept, we analyze the performance of BrainFrame on different experiment instances of a state-of-the-art neuron model, representing the inferior-olivary nucleus using a biophysically-meaningful, extended Hodgkin-Huxley representation. The model instances take into account not only the neuronal-network dimensions but also different network-connectivity densities, which can drastically affect the workload's performance characteristics. Main results. The combined use of different HPC technologies demonstrates that BrainFrame is better able to cope with the modeling diversity encountered in realistic experiments while at the same time running on significantly lower energy budgets. Our performance analysis clearly shows that the model directly affects performance and all three technologies are required to cope with all the model use cases. Significance. The BrainFrame framework is designed to transparently configure and select the appropriate back-end accelerator technology for use per simulation run. The PyNN integration provides a familiar bridge to the vast number of models already available. Additionally, it gives a clear roadmap for extending the platform support beyond the proof of concept, with improved usability and directly useful features to the computational-neuroscience community, paving the way for wider adoption.

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Brain modeling has been receiving significant attention over the years, both for its neuroscientific potential and for its challenges in the context of high-performance computing. The development of physiologically plausible neuron models comes at the cost of increased complexity. In this work, we have selected a highly computationally demanding model of the Inferior-Olivary Nucleus (InfOli) based on the Hodgkin-Huxley (HH) neuron model. This brain region, functionally coupled with the cerebellum, is of vital importance for motor skills and time-sensitive cognitive functions. The computing fabric of choice is an Intel Xeon/Xeon Phi system, which is a typical node of modern computing infrastructure. The target application is parallelized with various combinations of MPI and OpenMP and performance is measured on the target platform. The different implementations are compared and the best one is chosen. Further optimization of this implementation is presented in detail. Its behaviour is then examined when scaling up to neuron populations representative of realistic, human Inferior-Olivary neuronal networks. The evaluation's results highlight the importance of examining a network's size and density before choosing the best platform for its simulation. All the parallelization and vectorization options presented in the current paper are available on a public repository for further examination.@en

The development of physiologically plausible neuron models comes with increased complexity, which poses a challenge for many-core computing. In this work, we have chosen an extension of the demanding Hodgkin-Huxley model for the neurons of the Inferior Olivary Nucleus, an area of vital im-portance for motor skills. The computing fabric of choice is an Intel Xeon-Xeon Phi system, widely-used in modern computing infrastructure. The target application is paral-lelized with combinations of MPI and OpenMP. The best configurations are scaled up to human InfOli numbers.@en

Biologically accurate neuron simulations are increasingly important in research related to brain activity. They are computationally intensive and feature data and task parallelism. In this paper, we present a case study for the mapping of a biologically accurate inferior-olive (InfOli), neural cell simulator on an many-core research platform. The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The target neurons provide a major input to the cerebellum and are involved in motor skills and space perception. We exploit task-and data-partitioning, scaling the simulation over more than 40,000 neurons. The voltage-and frequency-scaling capabilities of the chip are explored, achieving more than 20% energy savings with negligible performance degradation. Four platform configurations are evaluated and a mapping with balanced workload and constant voltage and frequency is formally derived as optimal.@en

Biologically accurate neuron simulations are increasingly important in research related to brain activity. They are computationally intensive and feature data and task parallelism. In this paper, we present a case study for the mapping of a biologically accurate inferior-olive (InfOli), neural cell simulator on an many-core research platform. The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The target neurons provide a major input to the cerebellum and are involved in motor skills and space perception. We exploit task-and data-partitioning, scaling the simulation over more than 40,000 neurons. The voltage-and frequency-scaling capabilities of the chip are explored, achieving more than 20% energy savings with negligible performance degradation. Four platform configurations are evaluated and a mapping with balanced workload and constant voltage and frequency is formally derived as optimal.@en

Biologically accurate neuron simulations are increasingly important in research related to brain activity. They are computationally intensive and feature data and task parallelism. In this paper, we present a case study for the mapping of a biologically accurate inferior-olive (InfOli), neural cell simulator on an many-core research platform. The Single-Chip Cloud Computer (SCC) is an experimental processor created by Intel Labs. The target neurons provide a major input to the cerebellum and are involved in motor skills and space perception. We exploit task-and data-partitioning, scaling the simulation over more than 40,000 neurons. The voltage-and frequency-scaling capabilities of the chip are explored, achieving more than 20% energy savings with negligible performance degradation. Four platform configurations are evaluated and a mapping with balanced workload and constant voltage and frequency is formally derived as optimal.@en

In-vivo and in-vitro experiments are routinely used in neuroscience to unravel brain functionality. Although they are a powerful experimentation tool, they are also time-consuming and, often, restrictive. Computational neuroscience attempts to solve this by using biologically-plausible and biophysically-meaningful neuron models, most prominent among which are the conductance-based models. Their computational complexity calls for accelerator-based computing to mount large-scale or real-time neuroscientific experiments. In this paper, we analyze and draw conclusions on the class of conductance models by using a representative modeling application of the inferior olive (InfOli), an important part of the olivocerebellar brain circuit. We conduct an extensive profiling session to identify the computational and data-transfer requirements of the application under various realistic use cases. The application is, then, ported onto two acceleration nodes, an Intel Xeon Phi and a Maxeler Vectis Data Flow Engine (DFE). We evaluate the performance scalability and resource requirements of the InfOli application on the two target platforms. The analysis of InfOli, which is a real-life neuroscientific application, can serve as a useful guide for porting a wide range of similar workloads on platforms like the Xeon Phi or the Maxeler DFEs. As accelerators are increasingly populating High-Performance Computing (HPC) infrastructure, the current paper provides useful insight on how to optimally use such nodes to run complex and relevant neuron modeling workloads.@en

As aggressive integration paves the way for performance enhancement of many-core chips and technology nodes go below deca-nanometer dimensions, system-wide failure rates are becoming noticeable. Inevitably, system designers need to properly account for such failures. Checkpoint/Restart (C/R) can be deployed to prolong dependable operation of such systems. However, it introduces additional overheads that lead to performance variability. We present a versatile dependability manager (DepMan) that orchestrates a many-core application-level C/R scheme, while being able to follow time-varying error rates. DepMan also contains a dedicated module that ensures on-the-fly performance dependability for the executing application. We evaluate the performance of our scheme using an error injection module both on the experimental Intel Single-Chip Cloud Computer (SCC) and on a commercial Intel i7 general purpose computer. Runtime checkpoint interval optimization adapts to a variety of failure rates without extra performance or energy costs. The inevitable timing overhead of C/R is reclaimed systematically with Dynamic Voltage and Frequency Scaling (DVFS), so that dependable application performance is ensured.@en