Due to the severe cost pressure of consumer electronics, a migration to an advanced nanoscale CMOS processes, which is primarily developed for fast and low-power digital circuits operating at low supply voltages, is necessary, but it forces wireless RF transceivers to exploit more and more digital circuitry. These basic CMOS properties tend to coerce the design of wireless functions towards the digital domain where transistors are utilized as switches rather than current sources. Within the past decade, there have been tremendous efforts towards implementing fully-digital or digitally-intensive RF transmitters in which they demonstrate transmitter designs that operate from baseband up to the pre-power amplifier (PA) stage entirely in the digital domain. In view of this digitalization, the RF transmitter modulator, being the nearest to the antenna as it converts digital baseband modulation samples into an RF waveform, is considered the most critical building block of the transmitter, and it can be in the form of either a polar, Cartesian (I/Q), or an outphasing topology. For wide modulation bandwidths, due to their direct linear summation of the in-phase (I) and quadrature-phase (Q) signals and thus the avoidance of the bandwidth expansion, Cartesian modulators are substantiated as the most appropriate choice over their polar or outphasing counterparts. Since the effective modulating sample resolution is the utmost important parameter as it directly impacts the achievable dynamic range, linearity, error vector magnitude (EVM), noise floor, and out-of-band spectral emission, this thesis proposes a wideband, high-resolution, all-digital orthogonal I/Q radio-frequency digital-to-analog (RF-DAC). Chapter 1 briefly provides an overview of the conventional RF radio building blocks. It is discussed that contemporary RF transceivers must support most of multi-mode/multiband communication standards such as Wi-Fi, Bluetooth, and Fourth Generation (4G) of 3GPP cellular. In Chapter 2, four types of RF transmitter architectures have been briefly described. The analog I/Q modulators are the most straightforward and widely employed RF transmitters. They are later replaced by analog polar counterparts to address their poor power efficiency and noise performance. On the other hand, in the analog polar RF transmitters, their related amplitude and phase signals must be aligned or spectral regrowth is inevitable. Utilizing digitally intensive polar RF transmitters mitigates the latter alignment issue. Nonetheless, polar transmitters suffer from an additional issue that is related to their nonlinear conversion of in-phase and quadrature-phase signals into the amplitude and phase representation. Therefore, the polar RF transmitters are not able to manage very large baseband bandwidth of the most stringent communication standards, therefore, reusing I/Q modulators based on digitally intensive implementation appears to be a reasonable approach to resolve this issue. The digital I/Q RF transmitters, however, suffer again from inadequate power efficiency. Moreover, the combination of in-phase and quadrature phase paths must be orthogonal to produce an undistorted-upconverted-modulated RF signal. In Chapter 3, a novel all-digital I/Q RF modulator is described. Employing an upconverting RF clock with a 25% duty cycle ensures the orthogonal summation of Ipath and Qpath, which avoids nonlinear signal distortion. It was clarified that electric summing of I and Q digital unit array switches is the most appropriate I/Q orthogonal summation approach. Moreover, to address all four quadrants of the constellation diagram, the differential quadrature upconverting RF clocks must be utilized. In addition, it was explained that employing switches instead of utilizing current sources leads to superior noise performance of the all-digital I/Q transmitter. In Chapter 4, a novel 2×3-bit all-digital I/Q (Cartesian) RF transmit modulator is implemented which operates as an RF-DAC. The modulator performs based on the concept of orthogonal summing, which is introduced and elaborated in Chapter 3. It is based on a time-division duplexing (TDD) manner of an orthogonal I/Q addition. By employing this method, a very simple and compact design featuring high-output power, power-efficiency and low-EVM has been realized. The resolution of the experimental RF-DAC presented in this work is only 3-bit (including one sign bit), but it will be demonstrated in the following chapters that the resolution can be increased to 8–12 bits in an unequivocal manner for utilization in multi-standard wireless applications. In Chapter 5, the system design considerations of the proposed high-resolution, wideband all-digital I/Q RF-DAC are discussed. It is demonstrated that the upsampling clock frequency (fCKR), DRAC resolution (Nb), and memory length (lmem) are three important parameters that affect the dynamic performance of the proposed RF-DAC. Based on system level simulation results and the limitation in implementing the RF-DAC test-chip, they are designated as fCKR=300 MHz, Nb=12 bit, and lmem=8 k-word. The effect of these parameters on the in-band as well as out-of-band performance of RF-DAC are investigated. It is concluded that exploiting 13 bits of resolution for quadrature baseband signals is sufficient to meet the most stringent communication requirements. In Chapter 6, the theory and the design procedure of an innovative, differential, orthogonal power combining network, which is employed in the proposed all-digital modulator, is thoroughly explained. It is demonstrated that, in order to maintain an orthogonal operation between the in-phase and quadrature-phase paths, the effect of the power combiner on the in-phase and quadrature-phase paths must be considered, otherwise, the linear summation will not occur. As a result, the EVM and linearity performance will diminish. The power combiner consists of a transformer balun as well as its related programmable primary and secondary shunt capacitors. In order to achieve high efficiency at full power of operation, a class-E type matching network is adopted and subsequently modified in order to obtain a minimum modulation error. A switchable cascode structure is exploited to mitigate a reliability issue as well as to perform a mixer operation. Moreover, utilizing a switchable cascode structure also improves the isolation between quadrature paths. Furthermore, it is explained that the power combiner efficiency is primarily related to the transformer balun efficiency. A procedure is introduced in order to design an efficient, compact balun transformer. Also, it is explained that the RF-DAC operates as a class-B power amplifier at the power back-off levels. As a result, its performance in the power back-off region is lowered. In Chapter 7, the implemented wideband, 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65-nm CMOS is presented. Employing the orthogonal I/Q combining approach which is proposed in Chapter 3 guarantees the isolation between in-phase and quadrature-phase paths. The 4×f0 off-chip single-ended clock is converted to a differential version employing an on-chip transformer. The wide swing, low phase noise, high-speed dividers are incorporated to translate the 4×f0 differential clock to the fundamental frequency of f0. In the meantime, the complementary quadrature sign bit is used to address four quadrants of the related constellation diagram. The 25% differential quadrature clocks are generated using logic-AND operation between 2×f0 differential clock and f0 differential quadrature clocks. The 12-bit DRAC is implemented employing a segmentation approach, which consists of 256 MSB and 16 LSB thermometer unit cells. The layout arrangement of the DRAC unit cell proves to be very crucial. It was concluded that the vertical layout would be the most appropriate selection. The LO leakage and I/Q image rejection technique as well as two DPD memoryless techniques of AM-AM/AM-PM and constellation mapping are introduced, which will be extensively utilized in the measurement segment. In Chapter 8, the high-resolution wideband 2×13-bit all-digital I/Q transmitter, which was introduced in Chapter 7, is thoroughly measured. First, the chip is tested in continuouswave mode operation. It is demonstrated that, with a 1.3V supply and, of course, an on-chip power combiner, the RF-DAC chip generates more than 21dBm RF output power within a frequency range of 1.36–2.51 GHz. The peak RF output power, overall system, and drain energy efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below -160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and LO leakage of -65 dBc and -68 dBc, respectively. The RF-DAC could be linearized employing either of the two digital predistortion (DPD) approaches: memoryless polynomial or a lookup table. Its linearity is examined utilizing 4/16/64/256/1024-QAM baseband signals while their related modulation bandwidth can be as high as 154 MHz. Using AM-AM/AM-PM DPD improves the linearity by more than 25 dB while the measured EVM is better than -28 dB. Moreover, the constellation-mapping DPD is applied to the RF-DAC which improves linearity by more than 19 dB. These numbers indicate that this innovative concept is a viable option for the next generations of multi band/multi-standard transmitters. The realized demonstrator can perform as an energy-efficient RF-DAC in a stand-alone digital transmitter directly (e.g., for WLAN) or as a pre-driver for high-power basestation PAs. Chapter 9 draws the conclusions of the this thesis work and provides recommendations for future research and directions in the field of all-digital RF transmitters for wireless communication applications.