Interface fracture properties are increasingly requested in electronic packaging, be it for design problems or reliability issues. We demonstrate an induced delamination of the epoxy molding compound and die silicon interface, and propose a mixed mode chisel testing setup (MMC) and its experimental procedure. The MMC addresses several drawbacks of existing methods. The work includes samples from package fabrication processes and the establishing of critical fracture mechanics properties through finite element simulation the setup allows for the investigation of interfaces at package scale.@en

Interfacial delamination has become one of the key reliability issues in the microelectronics of portable devices and therefore is getting more and more attention. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch in mechanical properties of the materials adjacent to the interface and also possible asymmetry of loading and geometry, usually the delamination propagates under mixed mode conditions. In this study, a modified mixed mode bending test using production line interface samples is proposed. The critical fracture properties are obtained by interpreting the experimental results through dedicated finite element modeling. The interface types being considered in the present work are between EMC's and copper lead frame. Keywords-fracture; delamination; testing@en

The rapid diversification in microelectronics forebodes more complex system integration, be it for denser function integration or a span of dimensions between various technologies. Products may include more features, perform faster and be cheaper. With these trends the amount of material layers is increasing. This challenges development to a faster rating of material pairings. Delamination is a major issue among the related reliability aspects. When the design or testing steps are accompanied by simulation, fracture mechanical descriptions are increasingly proving helpful. The parameters needed for simulation have to be measured and should be available for different fracture mode mix angles. We investigated the interfacial fracture toughness of the Epoxy Molding Compound (EMC) to Silicon interface. Although difficult to delaminate we could carry out measurements using the Mixed Mode Chisel setup (MMC) that allowed us to induce different stress states at the crack tip at various external load angles. The samples we derived from the molding process of embedded wafer level ball grid arrays. Therefore we were able to use samples made with the same process as in real packaging. The crack tip position was determined by analysis of displacement results by digital image correlation. In order to interpret the sample reaction for extracting fracture mechanical parameters, adequate numerical modeling and simulation was required. The experiments provided the parameters for the models. Establishing the residual stress state in the materials preceded the interface delamination simulation: a two step interpretation. Residual stresses cannot be neglected; indeed they are part of the challenges to delaminate this interface at all. We found energy release rates increasing with fracture mode mix, and such values close to pure tensile opening at the crack tip. We recommend to exclude data from short crack lengths and to carefully expose the sample flanks. The results promise to extend the available interfacial fracture data soon.@en

The present study deals with experimental investigation of the delamination toughness of EMC (epoxy molding compound) and Copper-leadframe interfaces. Test samples were directly obtained from the production line. EMC is attached on copper substrates with various surface treatments. Mixed mode bending experiments were performed under various temperature and moisture environments. The test procedure and some results were reported previously in ECTC08 and ECTC09 [1-2]. Recently, we studied the effect of delaminated surfaces in order to get better understanding of the established fracture toughness. Therefore, after the delamination experiments, some of the delaminated samples were subjected to various surface analyses (SEM, FIB, EDX). Two types of failure patterns are found depending on the loading mode mixture, and the environmental conditions. Firstly, depending on the type of copper surface treatment, pure interface delamination is observed for some of the interfaces. Here, we observed clean delaminated copper surfaces. The second type of failure is a combination of interface delamination and compound cracking. Here, it is found that after the separation of interfaces, some EMC remains on the copper surface. In this case the experiment results showed that the interface delamination and molding compound cracking combined failure occurs at relatively high force values.@en

An ongoing root cause of failure in microelectronic industry is interface delamination. In order to explore the risk of interface damage, FE simulations for the fabrication steps as well as for the testing conditions are generally made in the design stage.@en

As we face higher numbers of material layers in the increasingly complex Microsystems, the rating of layers reliability has to keep pace. Fracture mechanical descriptions are a big qualitative improvement when using simulation for design and reliability support, especially when looking at layer delamination. In order to simulate the interfacial fracture we urgently need to find empirical parameters, because the fracture parameters have to be verified as critical. Such experiments are difficult to carry out at the Silicon-to-Epoxy Molding Compound (EMC) interface. We are now able to do such investigations using the Mixed Mode Chisel (MMC) setup. In this paper we compare results of the Silicon-EMC interface for the in- and exclusion of thermal residual stresses in the simulations. The interface specimens are of package scale and are derived from the embedded wafer level molding process. We find the impact of thermal residual stresses crucial for the validity of fracture toughness values, and show relations to consider when using the MMC setup. We do not find any EMC residuals on the delaminated Silicon surface.@en

In semiconductor technologies thermally and electrically conductive adhesives are widely used to attach the die to the substrate. Focus of this work are Isotropic Conductive Adhesives (ICA) with a high amount of electrically conductive filler particles and the characterization of such materials.@en

Interfacial delamination has become one of the key reliability issues in the microelectronic industry and therefore is getting more and more attention. The analysis of delamination of a laminate structure with a crack along the interface is central to the characterization of interfacial toughness. Due to the mismatch in mechanical properties of the materials adjacent to the interface and also possible asymmetry of loading and geometry, usually the crack propagates under mixed mode conditions. The present study deals with delamination toughness measurements of an epoxy molding compound - copper lead frame interface as directly obtained from a real production process. As a consequence the specimen dimensions are relatively small and therefore a dedicated small-size test set-up was designed and fabricated. The test set-up allows transferring two separated loadings (mode I and mode II) on a single specimen. The set-up is flexible and adjustable for measuring specimens with various dimensions. For measurements under various temperatures and moisture conditions, a special climate chamber is designed. The "current crack length" is required for the interpretation of measurement results through FEM-fracture mechanics simulations. Therefore, during testing the "current crack length" is captured using a CCD camera and a micro deformation analysis system (MicroDac). The critical fracture properties are obtained by interpreting the experimental results through dedicated finite element modeling.@en