In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application requirements. The embedded memories are expected to utilize more than 60% of the chip area after 2009. In addition, future SoCs are believed to embed memories of increasing capacities. As a result, the overall SoC yield will be dominated by the memory yield. This trend may make the overall yield unacceptable, unless special measures have been taken. In this thesis we propose and classify DRAM specific fault models relevant for the state-of-the-art semiconductor technologies. We also define and validate a set of DRAM targeted march tests. In addition, we propose a methodology for deriving conditions and tests for linked memory faults. We also investigate the detection conditions for linked memory faults when one of the faults involved is an address decoder fault. Finally, we propose various optimizations for test time reduction and/or increased fault coverage. We aimed at high relevancy of the ideas proposed in this thesis. For as far as possible the fault models and the tests presented here are validated using real industrial products. Some of the concepts originally proposed by the author more than 10 years ago are still being widely used by the industry and referred to by the academia. For example, many industrial products did use or are still using March LR, one of the tests derived in this thesis, for testing their (embedded) memories.