Bond wire damage is one of the most common failure modes of metal-oxide semiconductor field-effect transistor (MOSFET) power devices in wire-welded packaging. This paper proposes a novel bond wire damage detection approach based on two-port network measurement by identifying the MOSFET source parasitic inductance (LS). Numerical calculation shows that the number of bond wire liftoffs will change the LS, which can be used as an effective bond wire damage precursor. Considering a power MOSFET as a two-port network, LS is accurately extracted from frequency domain impedance (Z−parameter) using a vector network analyzer under zero biasing conditions. Bond wire cutoff experiments are employed to validate the proposed approach for bond wire damage detection. The result shows that LS increases with the rising severity of bond wire faults, and even the slight fault shows a high sensitivity, which can be effectively used to quantify the number of bond wire liftoffs of discrete MOSFETs. Meanwhile, the source parasitic resistance (RS) extracted from the proposed two-port network measurement can be used for the bond wire damage detection of high switching frequency silicon carbide MOSFETs. This approach offers an effective quality screening technology for discrete MOSFETs without power on treatment.

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Silicon carbide (SiC) is a third-generation semiconductor material with many advantages, such as high thermal conductivity, high critical breakdown voltage, and high saturated electron drift velocity, which can increase the operating frequency of the power conversion system to more than 100kHz. In the high-frequency, the parasitic effect will significantly reduce the switching speed of the power devices, increase power consumption and influence the uniformity of current distribution. In this paper, we established the calculation nodes of each part of the SiC-MOSFET Half-bridge power module and used ANSYS Q3D software to extract the parasitic parameters. Die-Die, Die-DBC-1, Die-DBC-2 and hybrid interconnect package structures were designed to optimize the parasitic inductance. Simulation results indicated that the chip-DBC-1 structure can reduce the parasitic inductance about 30% compared with Chip-Chip structure and effectively control the uniformity of current density on two parallel diode chips (ΔLdiode <0.1%). In the meantime, an 3D model of partial bond wires broken were designed to get further insight into the variation of parasitic inductances. The correlation mechanism between the partial bond wires broken and inductance change of the D-S terminals current path was studied. The results showed that as the number of broken bond wires increases, the inductance of D-S terminals current path was increased gradually. Finally, by using two-port S-parameters measurement method to extract the inductances of the discrete power device, the experimental results indicated that when one or two bond wires were broken, the inductance of D-S terminals current path increased by 4.69% and 15.69%, respectively. Overview, a risk evaluation method for SiC power devices based on the variation of the parasitic parameters of the bond wire was established.@en