Radiation tolerance of electronic devices and systems is mandatory for defence and space applications. In order to increase this tolerance for CMOS FETs, different layout techniques such as enclosed layout transistors (ELTs) can be employed. In this paper, a regular layout transistor is compared with two ELTs, which have square and octagonal shaped gates. For this purpose, a test circuit in 180 nm device technology has been designed and fabricated. Experimental comparison of the same size transistors with different layouts is performed in terms of the impact of process variations, and radiation tolerance. It is concluded that ELTs with different shapes behave similarly under radiation at least upto a dose of 1 Mrad. Furthermore, octagonal shaped ELTs are slightly less impacted from process variations in regard to square ELTs.

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal-oxide-semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%.

In this paper, a metal-oxide-semiconductor-field-effect-transistor modeling methodology for cryogenic conditions has been extensively verified through device measurements performed on a cryogenic probe station that was cooled by liquid nitrogen (-196 °C). The approach is valid for all operating regions (including the sub-threshold mode). The developed model can estimate I _D - V _GS and I _D-V _DS curves of transistors having different channel lengths and widths with an error of less than 5%. Statistical analysis of cryogenic measurements is used to introduce the variation levels around the nominal cryogenic operation to identify the impact of process variations at cryogenic conditions. Models adjusted to various temperatures between -196 °C and -40 °C have been developed for applications requiring different cryogenic operation conditions. Experimental data collected from a ring oscillator is employed to visualize the model performance in estimating the cryogenic characteristics of a typical integrated circuit. It is shown that the frequency of the ring oscillator is correctly simulated using the proposed cryogenic models.