The goal of this work described in this thesis is to design a CMOS image sensor chip, implementing pixels with a 4.8?m pitch with a peripheral readout circuitry in a 110nm CMOS process. The architecture of the CMOS image sensor is presented, with a functional illustration for every block. The 8T global shutter pixel noise, circuit and layout are described and analyzed in the thesis. The simulation results of the pixel readout speed and the output swing are presented and some other performances are shown. The Analog Front-End (AFE) circuit design of a switched capacitor amplifier and a sample and hold stage are also presented. The layout of the AFE circuit for the important blocks is done and the practical concerns of the amplifier design are discussed. The Low Voltage Differential Signaling (LVDS) driver also is implemented in this thesis, the power efficiency and common mode feedback stability issues of it are tackled as well. The simulation results of the LVDS driver with extraction of parasitics are presented and the performance summary is given.