Superconducting nanowire single-photon detectors (SNSPDs), owing to their unique performance, are currently the standard detector in most demanding single-photon experiments. One important metric for any single-photon detector is the recovery time, which defines the minimum temporal separation between consecutive detection events. In SNSPDs, the recovery time is more subtle, as the detection efficiency does not abruptly drop to zero when the temporal separation between detection events gets smaller, instead, it increases gradually as the SNSPD current recovers. SNSPD's recovery time is dominated by its kinetic inductance, the readout impedance, and the degree of saturation of internal efficiency. Decreasing the kinetic inductance or increasing the readout impedance can accelerate the recovery process. Significant reduction of the SNSPD recovery time, by, for example, adding a series resistor in the readout circuitry, is possible but can lead to detector latching, which hinders further detector operation or enforces underbiasing and hence a reduction in detection efficiency. Previous research has demonstrated passive resistive networks for the reduction of recovery time that rely on trial and error to find the appropriate resistance values. Here, we show that, using a cryogenically compatible and tunable resistor technology, one can find the optimized impedance values, delivering fast SNSPD recovery time while maintaining maximum internal detection efficiency. Here, we show an increase of around twofold in both maximum achievable detection rates and the achievable detection efficiency at high photon fluxes, demonstrating detection rates close to 114 Mcps with no loss of internal detection efficiency.

Due to stringent thermal budgets in cryogenic technologies such as superconducting quantum computers and sensors, electronic building blocks that simultaneously offer low energy consumption, fast switching, low error rates, a small footprint, and simple fabrication are pivotal for large-scale devices. Here, we demonstrate a superconducting switch with attojoule switching energy, high speed (pico-second rise/fall times), and high integration density (on the order of 10 ^-2 μm ² per switch). It consists of a superconducting nanochannel and a metal heater separated by an insulating silica layer. We experimentally demonstrate digital gate operations utilizing these nanostructures, such as NOT, NAND, NOR, AND, and OR gates, with a few femtojoules of energy consumption and ultralow bit error rates <10 ^-8. In addition, we build energy-efficient volatile memory elements with nanosecond operation speeds and a retention time over 10 ⁵ s. These superconducting switches open new possibilities for increasing the size and complexity of modern cryogenic technologies.