This paper presents a power-centric systems-engineering approach for PlanarSats and for atto-, and femto-class spacecraft where surface-limited power dominates design. We review agency practices (The National Aeronautics and Space Administration (NASA), European Space Agency (ESA), Japan Aerospace Exploration Agency (JAXA)) and the American Institute of Aeronautics and Astronautics (AIAA) framework, then extend them with refined low-power subcategories and a log-linear method for selecting phase- and class-appropriate power contingencies. The method is applied to historical and conceptual PlanarSats to show how contingencies translate into required array area, allowable incidence angles, and duty cycle, linking power sizing to geometry and operations. We define the operational power envelope as the range of satellite orientations and conditions under which generated power meets or exceeds mission requirements. Consistent with agency guidance, sizing is performed to the maximum expected value (MEV) (CBE plus contingency); when bounding or stress analyses are needed, we report the maximum possible value (MPV) (Maximum Possible Value) by applying justified system-level margins to the MEV. Results indicate that disciplined, phase-aware contingency selection materially reduces power-related risk and supports reliable, scalable PlanarSat missions under severe physical constraints.

Sporadic-E (Es) layers can strongly perturb HF/VHF propagation and create intermittent interference, motivating higher-revisit monitoring at the frequencies most affected. EsTRACE (Es-layer TRAnsient Cloud Explorer) is a PlanarSat mission concept that transmits sequential beacons in the 28/50 MHz amateur bands using FT4 (weak-signal digital) and CW (continuous wave) waveforms and leverages distributed amateur receiver networks for near-real-time SNR mapping. This paper documents the early-phase spacecraft design from the Bid/proposal phase (Bid), through the Conceptual Design Review (CoDR), to the Preliminary Design Review (PDR), using a power-first sizing loop that couples link-budget closure to duty cycle and solar-array area under a free-tumbling, batteryless constraint. The analysis supports conceptual feasibility of the architecture under stated antenna and ground-segment assumptions; on-orbit demonstration and measured RF/antenna characterization are identified as required future validation steps.

This paper introduces a power-driven systems engineering methodology for the early-phase design of highly miniaturized satellites: PlanarSats. We derive an analytical framework linking power requirements, contingency policies, solar-cell performance, and subsystem integration to determine the absolute minimum satellite size. Through idealized and detailed case studies, we explore the trade-offs inherent in subsystem selection and integration constraints. Sensitivity analysis identifies critical factors affecting minimum area and operational envelopes. Our framework provides a clear tool for balancing functionality, reliability, and physical limits in next-generation ultra-small satellite missions.

As satellite technology advances, there has been a notable trend towards miniaturization, leading to the development of increasingly smaller satellites such as femtosatellites and attosatellites. A new emerging form of such satellites is often called ChipSat, with unique designs that utilize both surfaces of a single plane to maximize functionality within limited dimensions. Initially, the term ChipSat referred to system–on–a–chip satellites but it has since expanded to include centimeter and millimeter scale spacecraft. To provide a clearer terminology, this paper introduces the term “PlanarSat” for such a planar spacecraft. Despite the challenges in deployment and the constraints, such as cost, size, access to space, and capabilities, of miniaturized subsystems, these satellites represent a significant shift in space technology, aiming for cost-effective solutions and innovative mission capabilities. This study reviews thirty sub-100-gram satellites, analyzing their design, deployment, and potential for future advancements in a comparative manner. In this study, satellite independence was defined based on system-wise independence, highlighting operational autonomy irrespective of physical connections. The survey’s findings highlight technological advancements and potential applications for these very small spacecraft, which are pushing the boundaries of what is feasible with smaller satellites and how these satellites were or planned to be delivered to orbit. The analysis results provide a basic cost comparison, providing information on hardware and launch costs, taking the instantaneous data rate as a reference point, underscoring the need for a new systems engineering approach to the design of such satellites.

A CdZnTe based semiconductor X-ray detector (XRD) and its associated readout electronics has been developed by the Space Systems Design and Testing Laboratory of Istanbul Technical University and the High Energy Astrophysics Detector I-Aboratory of Sabanci University along with an SME partner. The XRD will be the secondary science mission on board BeEagleSat, which is developed as one of the double CubeSats for the QB50 project. QB50 is a European Framework 7 projcct carried out by a number of international organizations led by the von Karman Institute of Belgium. The heart of the XRD is a 2.5 mm thick, 15 mm x 15 mm CdZnTe crystal with orthogonal electrode strips on top and bottom for position resolution on the crystal. There are 3 sets of steering electrodes in between anodes. A commercial off the shelf (COTS) high voltage source provides necessary potential difference to transport electrons and holes towards electrodes. The signals from each strip are read by a COTS ASIC, RENA-3b, controlled my MSP 430. The XRD board (single -10 cm x 10 cm board) also carries the necessary power regulators and 7 COTS batteries. In a previous paper presented at the IAC 2014, we discussed the main design of the XRD and provided results from some of the early vibration tests of the mechanical design. At the time, the CdZnTe crystal has not been attached, and the readout electronics and software were still in development phase. In this paper, we present the laboratory performance of the electronic readout system and discuss the current phase of the XRD development.